1. The Field of the Invention
The present invention relates to the formation of semiconductor devices. In particular, the present invention relates to the formation of isolation trench structures for semiconductor devices. More particularly, the present invention relates to an inventive method for the formation of an inventive isolation microtrench at the edge of a field oxide region of a semiconductor device.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductor substrates described above.
The term "substrate assembly" is intended herein to mean a semiconductor substrate having one or more layers or structures formed thereon. As such, the substrate assembly may be, by way of example and not by way of limitation, a semiconductor substrate such as, N-well or P-well doped silicon having a gate oxide layer over an active area of the semiconductor substrate, a field oxide layer adjacent to the gate oxide layer, and a microtrench positioned between the gate oxide layer and the field oxide layer.
In the microelectronics industry, the process of miniaturization entails shrinking the size of individual semiconductor devices to make room for more semiconductor devices on a given unit area. With miniaturization, problems of proper isolation between semiconductor devices arise. When miniaturization demands the shrinking of individual devices, isolation structures must also be reduced in size. Attempts to isolate semiconductor devices from each other are currently limited to photolithographic limits of about 0.35 microns for isolation structure widths.
To form an isolation trench on a semiconductor wafer by photolithography, for example, the photoresist mask through which the isolation trench is etched generally utilizes a beam of light, such as ultraviolet (UV) light, to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than the semiconductor wafer on which the photoresist coating is located. Light is shone through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the size of the photolithographic coating and that develops the portions of the photoresist coating that are unmasked and are intended to remain. The undeveloped portions are thereafter easily removed.
The resolution with which a pattern can be transferred to the photoresist coating from the photolithographic template is currently limited in commercial applications to widths of about 0.35 microns or greater. In turn, the dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming isolation trenches that have a size that is reduced from what can be formed with conventional photolithography.
The photolithography limit and accompanying problems of alignment and contamination are hindrances upon the ever-increasing pressure in the industry to miniaturize. Other problems that occur in isolation trench formation are, with trenches that are deep and wide in comparison to the size of the individual device that the trench is isolating, dielectric material such as thermal silicon oxide that fills the trench tends to encroach upon the active area that the trench is supposed to isolate. Another problem is that wide and deep trenches tend to put a detrimental amount of stress upon the silicon of the active area that leads to defects such as delamination, fracture, and device failure.
Another problem that arises in isolation trench formation under current photolithographic limits is that with the limitations of trench widths, specific defects arise at the upper comers of the active areas. One such defect is called a Kooi corner defect. Removal of a Kooi defect requires growing a sacrificial oxide (SAC) and then subsequently removing it before a gate oxide can be grown over an active area. SAC growth can destructively remove substantially all semiconductive material, such as silicon, down to or near the bottom of the trench that has just been fabricated, thereby neutralizing the effect of trench formation. It would be an advancement in the art to find a method to avoid this defect. At the field edge of a LOCOS in silicon, there is a stress-induced defect upon growth of the LOCOS. The oxide thickness is thinner in a small space and thicker in a large space. Thus, with a small space, there exists difficulty in forming an isolation region because of the potential extent of growth of a LOCOS into the isolation region. A microtrench that avoids both the Kooi defect and the problems associated with growing a LOCOS would therefore be an advancement in the art
What is needed is an inventive method of isolation trench formation that avoids the problems of the prior art such as alignment, photolithographic limitations, isolation trench filling that causes stress upon the active areas, and SAC processing that substantially neutralizes the effect of the isolation trench that is formed.